将VHDL语言转换成Verilog HDL语言

发布网友发布时间：2022-04-26 06:57

共2个回答

热心网友时间：2022-06-24 23:55

有个小软件可以完成vhdl和verilog的语法转化叫x-hdl
http://ishare.iask.sina.com.cn/f/36981321.html

mole cnt99(clk, rst, en, cq, LED1, LED2, cout);
input clk;
input rst;
input en;
input [6:0] cq;
input [3:0] LED1;
input [3:0] LED2;
output cout;
reg cout;

always @(posedge clk or posedge rst or en)
begin: xhdl0
reg [3:0] cqi;
reg [6:0] cqii;
reg [3:0] hi;
if (rst == 1'b1)
begin
cqi = {4{1'b0}};
hi = {4{1'b0}};
end
else
begin
if (en == 1'b1)
begin
if (hi < 9)
begin
if (cqi < 9)
cqi = cqi + 1;
else
begin
cqi = {4{1'b0}};
hi = hi + 1;
end
end
else
hi = {4{1'b0}};
if (cqii < 99)
cqii = cqii + 1;
else
cqii = {7{1'b0}};
end
end
if (cqi == 9 & hi == 9)
cout <= 1'b1;
else
cout <= 1'b0;
cq <= cqii;
LED1 <= hi;
LED2 <= cqi;
end

endmole

热心网友时间：2022-06-24 23:55

mole cnt99(clk, rst, en, cq, LED1, LED2, cout);
input clk;
input rst;
input en;
output [6:0] cq;
reg [6:0] cq;
output [3:0] LED1;
reg [3:0] LED1;
output [3:0] LED2;
reg [3:0] LED2;
output cout;
reg cout;

always @(posedge clk or posedge rst or en)
begin: xhdl0
reg [3:0] cqi;
reg [6:0] cqii;
reg [3:0] hi;
if (rst == 1'b1)
begin
cqi = {4{1'b0}};
hi = {4{1'b0}};
end
else
begin
if (en == 1'b1)
begin
if (hi < 9)
begin
if (cqi < 9)
cqi = cqi + 1;
else
begin
cqi = {4{1'b0}};
hi = hi + 1;
end
end
else
hi = {4{1'b0}};
if (cqii < 99)
cqii = cqii + 1;
else
cqii = {7{1'b0}};
end
end
if (cqi == 9 & hi == 9)
cout <= 1'b1;
else
cout <= 1'b0;
cq <= cqii;
LED1 <= hi;
LED2 <= cqi;
end

endmole