verilog怎么控制iic的读写,怎么控制多个数据的。。求大神
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发布时间：2022-04-24 11:03
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热心网友
时间：2023-10-10 17:44
//`timescale 1ns / 1ps
mole i2c_control(
clk,
i2c_sclk,
i2c_sdat,
i2c_data,
start,
tr_end,
ack,
rst,
counter,
sdo);
input clk;
input [23:0]i2c_data;
input start;
input rst;
//input w_r;
inout i2c_sdat;
output i2c_sclk;
output tr_end;
output ack;
output [5:0]counter;
output sdo;
reg sdo;
reg sclk;
reg tr_end;
reg [23:0]sd;
reg [5:0]counter;
assign i2c_sclk=sclk |(((counter>=4)&(counter<=30))?~clk:0);
assign i2c_sdat=sdo?1'bz:0;
reg ack1,ack2,ack3;
wire ack=ack1 |ack2 |ack3;
always@(negedge rst or posedge clk)begin
if(!rst)counter<=6'b111111;
else begin
if(start==0)
counter<=0;
else
if(counter<6'b111111)counter<=counter+1;
end
end
always@(negedge rst or posedge clk)begin
if(!rst)begin sclk<=1;sdo<=1;ack1<=0;ack2<=0;ack3<=0;tr_end<=0;end
else
case(counter)
6'd0 :begin ack1<=0;ack2<=0;ack3<=0;tr_end<=0;sdo<=1;sclk<=1;end
6'd1 :begin sd<=i2c_data;sdo<=0;end
6'd2 :sclk=0;
6'd3 :sdo<=sd[23];
6'd4 :sdo<=sd[22];
6'd5 :sdo<=sd[21];
6'd6 :sdo<=sd[20];
6'd7 :sdo<=sd[19];
6'd8 :sdo<=sd[18];
6'd9 :sdo<=sd[17];
6'd10 :sdo<=sd[16];
6'd11 :sdo<=1'b1;
6'd12 :begin sdo<=sd[15];ack1<=i2c_sdat;end
6'd13 :sdo<=sd[14];
6'd14 :sdo<=sd[13];
6'd15 :sdo<=sd[12];
6'd16 :sdo<=sd[11];
6'd17 :sdo<=sd[10];
6'd18 :sdo<=sd[9];
6'd19 :sdo<=sd[8];
6'd20 :sdo<=1'b1;
6'd21 :begin sdo<=sd[7];ack2<=i2c_sdat;end
6'd22 :sdo<=sd[6];
6'd23 :sdo<=sd[5];
6'd24 :sdo<=sd[4];
6'd25 :sdo<=sd[3];
6'd26 :sdo<=sd[2];
6'd27 :sdo<=sd[1];
6'd28 :sdo<=sd[0];
6'd29 :sdo<=1'b1;
6'd30 :begin sdo<=1'b0;sclk<=1'b0;ack3<=i2c_sdat;end
6'd31 :sclk<=1'b1;
6'd32 :begin sdo<=1'b1;tr_end<=1;end
endcase
end
endmole
热心网友
时间：2023-10-10 17:44
