用VERILOG做个分频器，输入50MHZ,，要求输出一个4HZ，一个1MHZ的分频器，怎么弄啊

发布网友发布时间：2022-04-24 17:50

共3个回答

热心网友时间：2023-10-28 09:47

这是个分频的模块
mole clk434(clkin,clkout);
input clkin;
output clkout;

reg [8:0]num;
reg clkout;

always @(posedge clkin)
begin
if(num==324)num=0; ----只需要修改这里的324和下面的162就行了
else num=num+1; ----- 比如50M分1MHz，clkin=50M，50000000/1000000=50,就把324改为50，162改为50/2=25.
if(num>162)clkout=1;
else clkout=0;
end
endmole

热心网友时间：2023-10-28 09:47

mole led(rst,clk_50M,clk_4,clk_1M);
input rst,clk_50M;
output clk_4,clk_1M;

reg clk_4,clk_1M;
integer count_4,count_1M;

always @(posedge clk_50M or posedge rst)
begin
if (rst)
begin
clk_4 <= 0;
clk_1M <= 0;
count_4 <= 1;
count_1M <= 1;
end
else
begin
if (count_1M == 25)
begin
count_1M <= 1;
clk_1M <= !clk_1M;
end
else
count_1M <= count_1M + 1;
if (count_4 == 6_250_000)
begin
count_4 <= 1;
clk_4 <= !clk_4;
end
else
count_4 <= count_4 + 1;
end
end

endmole

热心网友时间：2023-10-28 09:48

这个程序能实现但是要修改一下:将!改为~