发布网友 发布时间:2022-05-06 16:47
共2个回答
热心网友 时间:2023-10-12 13:14
1.编辑输入VHDL程序并设为当前工程文件
设:clr为系统时钟,clr为异步清零控制端,load为同步置数控制端,date为同步置数数据输入端口,count为计数器输出端口
实体名为:add4b.VHD
2.编译设计文件并予仿真验证
VHDL程序:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY add4b IS
PORT(
date:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
load:IN STD_LOGIC;
clr:IN STD_LOGIC;
clk:IN STD_LOGIC;
count:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END ENTITY add4b;
ARCHITECTURE upcount OF add4b IS
BEGIN
upcount:PROCESS(clk,clr)
BEGIN
IF clr='1' THEN count<=x"0";
ELSIF rising_edge(clk) THEN
IF load='1' THEN count<=date;
ELSE count<= count +1;
END IF;
END IF;
END PROCESS upcount;
END upcount;
3.波形仿真
热心网友 时间:2023-10-12 13:15
牛 比我发问题还早 嘿嘿 O(∩_∩)O哈哈~热心网友 时间:2023-10-12 13:14
1.编辑输入VHDL程序并设为当前工程文件
设:clr为系统时钟,clr为异步清零控制端,load为同步置数控制端,date为同步置数数据输入端口,count为计数器输出端口
实体名为:add4b.VHD
2.编译设计文件并予仿真验证
VHDL程序:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY add4b IS
PORT(
date:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
load:IN STD_LOGIC;
clr:IN STD_LOGIC;
clk:IN STD_LOGIC;
count:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END ENTITY add4b;
ARCHITECTURE upcount OF add4b IS
BEGIN
upcount:PROCESS(clk,clr)
BEGIN
IF clr='1' THEN count<=x"0";
ELSIF rising_edge(clk) THEN
IF load='1' THEN count<=date;
ELSE count<= count +1;
END IF;
END IF;
END PROCESS upcount;
END upcount;
3.波形仿真
热心网友 时间:2023-10-12 13:15
牛 比我发问题还早 嘿嘿 O(∩_∩)O哈哈~