EDA的编程问题
发布网友
发布时间：2022-12-29 14:54
共3个回答
热心网友
时间：2023-10-26 21:09
library ieee;
use ieee.std_logic_1164.all;
entity yima is
port(g1,g2,a,b,c:in std_logic;
y:out std_logic_vector(7 downto 0));
end;
architecture art of yima is
signal data:std_logic_vector(2 downto 0);
begin
data<=c&b&a;
process(g1,g2,data)
begin
if g2='1' or g1='1' then
y<=(others=>'0');
else
case data is
when "000"=>y<="11111110";
when "001"=>y<="11111101";
when "010"=>y<="11111011";
when "011"=>y<="11110111";
when "100"=>y<="11101111";
when "101"=>y<="11011111";
when "110"=>y<="10111111";
when "111"=>y<="01111111";
when others=>null;
end case;
end if;
end process;
end art;
热心网友
时间：2023-10-26 21:09
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DECODE3_8 IS
PORT ( DIN : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
EN : IN STD_LOGIC;
XOUT : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END DECODE3_8;
ARCHITECTURE ONE OF DECODE3_8 IS
BEGIN
PROCESS (DIN, EN)
BEGIN
IF EN = ‘1’ THEN
IF DIN = “111” THEN XOUT <= “11111110”;
ELSIF DIN = “110” THEN XOUT <= “11111101”;
ELSIF DIN = “101” THEN XOUT <= “11111011”;
ELSIF DIN = “100” THEN XOUT <= “11110111”;
ELSIF DIN = “011” THEN XOUT <= “11101111”;
ELSIF DIN = “010” THEN XOUT <= “11011111”;
ELSIF DIN = “001” THEN XOUT <= “10111111”;
ELSE XOUT <= “11111011”;
END IF;
END PROCESS;
END ONE;
热心网友
时间：2023-10-26 21:09
