用VHDL语言编写 带进位输出的10进制计数器
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发布时间：2022-07-26 14:51
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时间：2023-10-21 00:08
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count is
port(clk:in std_logic;
c:buffer std_logic_vector(3 downto 0):="0000";
q:buffer std_logic_vector(3 downto 0));
end count;
architecture a of count is
begin
process(clk)
begin
if(clk'event and clk='1' )then
if q="1111" then
q<="0000";
c<=c+1;
else
q<=q+1;
end if;
end if;
end process;
end a;
(附：时序仿真图)
