在FPGA上制作一个9秒的计数器。
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发布时间：2022-10-13 18:20
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时间：2023-11-08 04:04
clock freq = 50MHz,
output freq = 1/9 Hz
counter width = ceil(log2(9*450*10^6)) = 29
CONSTANT cnt_norm : UNSIGNED(28 DOWNTO 0) := TO_UNSIGNED(9*450*(10**6)-1, 29);
SIGNAL counter : UNSIGNED(28 DOWNTO 0) := (OTHERS=>'0');
SIGNAL pulse : STD_LOGIC := '0';
cnt_proc: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF counter = cnt_norm THEN
counter <= (OTHERS=>'0');
pulse <= '1';
ELSE
counter <= counter + 1;
pulse <= '0';
END IF;
END IF;
END PROCESS;
