用vhdl语言写一个加减计数器
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发布时间：2022-06-25 02:29
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时间：2024-01-21 18:22
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY add_sub_counter IS
PORT ( clk,player1_in,player2_in : IN STD_LOGIC;
counter : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END;
ARCHITECTURE behaviour OF add_sub_counter IS
SIGNAL q : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
PROCESS(clk,player1_in,player2_in)
VARIABLE player : STD_LOGIC_VECTOR (1 DOWNTO 0);
BEGIN
player := player1_in&player2_in;
IF rising_edge(clk) THEN
CASE player IS
WHEN "10" => q <= q+1;
WHEN "01" => q <= q-1;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
counter <= q ;
END;
