四位串行移位寄存器设计的VHDL实现代码
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发布时间：2022-04-29 21:07
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时间：2022-06-22 20:52
use ieee.std_logic_1164.all;
entity mux4_1 is
port(d0,d1,d2,d3,a1,a2:in std_logic;
q:out std_logic);
end entity mux4_1;
architecture rtl of mux4_1 is
signal sel:std_logic_vector(1 downto 0);
begin
sel<=a1&a2;
process(sel) is
begin
case sel is
when "00"=>q<=d0;
when "01"=>q<=d1;
when "10"=>q<=d2;
when "11"=>q<=d3;
when others=>q<='X';
end case;
end process;
end architecture rtl;
