交通灯控制系统
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发布时间:2022-04-28 13:20
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热心网友
时间:2023-10-10 03:08
你改一下名称就好了
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hx is
port(clk:in std_logic;
A1,B1,C1,D1,A2,B2,C2,D2:out std_logic;
AR,AY,AG,BR,BY,BG,oe:out std_logic);
end hx;
architecture arch of hx is
type states is(s3,s2,s1,s0);
signal state:states:=s0;
signal next_state1:states:=s0;
signal count:std_logic_vector(2 downto 0);
signal count0:std_logic_vector(3 downto 0);
signal count1:std_logic_vector(3 downto 0);
signal data0:std_logic_vector(3 downto 0);
signal data1:std_logic_vector(3 downto 0);
signal light:std_logic_vector(5 downto 0);
signal en,load,carry:std_logic;
begin
p1:process(clk,load)
begin
if(rising_edge(clk))then
if load='1' then
count0<=data0;
elsif count0="0000"then
count0<="1001";
else
count0<=count0-'1';
end if;
end if;
end process p1;
p2:process(clk)
begin
if clk='0'then
if count0="0000"then
en<='1';
else
en<='0';
end if;
end if;
end process p2;
p3:process(clk,en)
begin
if(clk'event and clk='1')then
if en='1'then
if load='1'then
count1<=data1;
elsif count1="0000"then
count1<="0001";
else
count1<=count1-'1';
end if;
end if;
end if;
end process p3;
p4:process(clk)
begin
if(falling_edge(clk))then
if(count0="0000"and count1="0000")then
load<='1';
state<=next_state1;
else
load<='0';
--end if;
end if;
end if;
end process p4;
p5:process(state)
begin
case state is
when s0=>light<="001100";
next_state1<=s1;
data0<="0000";
data1<="0101";
when s1=>light<="010100";
next_state1<=s2;
data0<="0101";
data1<="0000";
when s2=>light<="100001";
next_state1<=s3;
data0<="0101";
data1<="0011";
when s3=>light<="100010";
next_state1<=s0;
data0<="0101";
data1<="0000";
end case;
end process p5;
A1<=count0(0);
B1<=count0(1);
C1<=count0(2);
D1<=count0(3);
A2<=count1(0);
B2<=count1(1);
C2<=count1(2);
D2<=count1(3);
oe<='0';
AR<=light(5);
AY<=light(4);
AG<=light(3);
BR<=light(2);
BY<=light(1);
BG<=light(0);
end arch;
热心网友
时间:2023-10-10 03:08
都是PLC控制的吧
热心网友
时间:2023-10-10 03:08
你改一下名称就好了
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hx is
port(clk:in std_logic;
A1,B1,C1,D1,A2,B2,C2,D2:out std_logic;
AR,AY,AG,BR,BY,BG,oe:out std_logic);
end hx;
architecture arch of hx is
type states is(s3,s2,s1,s0);
signal state:states:=s0;
signal next_state1:states:=s0;
signal count:std_logic_vector(2 downto 0);
signal count0:std_logic_vector(3 downto 0);
signal count1:std_logic_vector(3 downto 0);
signal data0:std_logic_vector(3 downto 0);
signal data1:std_logic_vector(3 downto 0);
signal light:std_logic_vector(5 downto 0);
signal en,load,carry:std_logic;
begin
p1:process(clk,load)
begin
if(rising_edge(clk))then
if load='1' then
count0<=data0;
elsif count0="0000"then
count0<="1001";
else
count0<=count0-'1';
end if;
end if;
end process p1;
p2:process(clk)
begin
if clk='0'then
if count0="0000"then
en<='1';
else
en<='0';
end if;
end if;
end process p2;
p3:process(clk,en)
begin
if(clk'event and clk='1')then
if en='1'then
if load='1'then
count1<=data1;
elsif count1="0000"then
count1<="0001";
else
count1<=count1-'1';
end if;
end if;
end if;
end process p3;
p4:process(clk)
begin
if(falling_edge(clk))then
if(count0="0000"and count1="0000")then
load<='1';
state<=next_state1;
else
load<='0';
--end if;
end if;
end if;
end process p4;
p5:process(state)
begin
case state is
when s0=>light<="001100";
next_state1<=s1;
data0<="0000";
data1<="0101";
when s1=>light<="010100";
next_state1<=s2;
data0<="0101";
data1<="0000";
when s2=>light<="100001";
next_state1<=s3;
data0<="0101";
data1<="0011";
when s3=>light<="100010";
next_state1<=s0;
data0<="0101";
data1<="0000";
end case;
end process p5;
A1<=count0(0);
B1<=count0(1);
C1<=count0(2);
D1<=count0(3);
A2<=count1(0);
B2<=count1(1);
C2<=count1(2);
D2<=count1(3);
oe<='0';
AR<=light(5);
AY<=light(4);
AG<=light(3);
BR<=light(2);
BY<=light(1);
BG<=light(0);
end arch;
热心网友
时间:2023-10-10 03:08
都是PLC控制的吧