请帮忙设计一个分频器，用VHDL语言写的。将40MHz的信号分成1hz与1000hz和2000hz

发布网友发布时间：2022-05-15 19:32

共1个回答

热心网友时间：2024-02-27 09:02

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity FENGPIN is
port(cp_32m,res: in std_logic;
sec,cp_xuan: out std_logic);
end MIAOCP;
architecture ART of FENGPIN is
begin
process(cp_32m,res) ---1 Hz分频
variable cnt:integer range 0 to 40000000;
begin
if res='1' then
cnt:=0;
elsif cp_32m'event and cp_32m='1' then
if cnt=32000000 then
cnt:=0;
sec<='1';
else cnt:=cnt+1;
sec<='0';
end if;
end if;
end process;
process(cp_32m,res) --1000Hz分频
variable cnt:integer range 0 to 40000;
begin
if res='1' then
cnt:=0;
elsif cp_32m'event and cp_32m='1' then
if cnt=1000000 then
cnt:=0;
cp_xuan<='1';
else cnt:=cnt+1;
cp_xuan<='0';
end if;
end if;
end process;
end ART;